1. Field of the Invention
Synchronization Equipment
The present invention relates to a synchronizing apparatus for use in the receiver of a digital communication system.
2. Description of the Related Art
Digitalization in communication has remarkably advanced lately and is still progressing. In digital communication, the receiving side needs means for pulling frame synchronization in with high speed and high precision.
A conventional synchronizing apparatus for pulling-in of synchronization employs a PLL (phase-locked loop) as described in xe2x80x9cHOW TO USE PLL-ICxe2x80x9d (written by Tuneyasu Hata and Kazuaki Furukawa, and published by Akiba, pp. 20-32, November 1976). With reference to FIG. 1, this apparatus has a digital VCO (voltage-controlled oscillator) 1 for finally producing a signal synchronized with an input signal under the control of the PLL, a binary quantizing phase comparator 2 for comparing the phase of the input signal with the phase of the output signal from the digital VCO 1, and producing data of +1 or xe2x88x921 as a result of the comparison, and a sequential loop filter 3 for counting the output signal from the binary quantizing phase comparator 2 and supplying a correction signal to the digital voltage-controlled oscillator 1 when the count exceeds a certain value (N). The binary quantizing phase comparator 2 includes a phase comparator 4 for comparing the phase of the input signal with the phase of the output signal from the digital VCO 1, and a quantizer 5 for quantizing the result from the comparator into a binary value. The digital VCO 1 includes a fixed oscillator 6 for oscillating at a fixed frequency, a pulse addition/removal circuit 7 for adding or removing a pulse to or from the output of the fixed oscillator 6 when the sequential loop filter 3 generates the output signal, and a frequency divider 8 for dividing the frequency of the output signal from the fixed oscillator 6 to or from which the pulse has been added or removed.
In this synchronizing apparatus, the phase comparator 4 of the binary quantizing phase comparator 2 compares the phase of the input signal with the phase of the output signal from the digital VCO 1. The quantizer 5 produces a value of xe2x88x921 when the phase of the output signal from the digital VCO 1 is larger than that of the input signal, or when the output signal is ahead of the input signal, but it produces a value of +1 when it is smaller than that, or when the output signal is behind the input signal. The sequential loop filter 3 counts the output from the quantizer 5, and supplies to the pulse addition/removal circuit 7 the correction signal for controlling a pulse to be removed when the count arrives at +N, or for controlling a pulse to be added when the count reaches xe2x88x92N.
Therefore, in this synchronizing apparatus used as a frame synchronizer, when the phase of the output signal from the digital VCO 1 shifts in the positive or negative direction relative to the phase of the frame synchronizing signal, the sequential loop filter 3 supplies the first correction signal N frames after the start of pulling-in of synchronization.
When the correction signal is supplied to the digital VCO 1, the pulse addition/removal circuit 7 inserts a pulse in the output signal from the fixed oscillator 6 or removes it therefrom in response to this correction signal. Since the oscillation frequency of the fixed oscillator 6 is selected to be R times as high as the input frequency in order that the quantized value for phase control can be reduced, the output signal from the fixed oscillator 6 in which a pulse has been inserted or from which a pulse has been removed by the pulse addition/removal circuit 7 is supplied to the frequency divider 8 where its frequency is divided by R, and the frequency-divided signal is produced from the output end of the digital VCO 1.
When there is still a phase difference between the output signal from the digital VCO 1 and the input signal even after the insertion or removal of a pulse, the above operations are repeated, and finally the output signal from the digital VCO 1 is controlled so that the phase difference between the output signal from the digital VCO 1 and the input signal can be minimized.
In this apparatus, if "PHgr" is the initial phase difference at the time of pulling-in of frame synchronization, the time in which the phase pulling-in is caused within an error xcex4 is given by the following equation (1)
TO={("PHgr"xe2x88x92xcex4)R/360}xc3x97Nxe2x80x83xe2x80x83(1)
where 360xc2x0/R is the phase change in one cycle.
The average time in which the frame synchronization is established is derived from Eq. (1) as in the following equation (2).
                              T          AVE                =                                            ∫              0              180                        ⁢                                          {                                                                            (                                              φ                        -                        δ                                            )                                                              360                      /                      R                                                        xc3x97                  N                                }                            ⁢                              ⅆ                φ                                              =                                    (                              0.25                -                                  δ                  /                  360                                            )                        ⁢                          xe2x80x83                        ⁢            N            ⁢                          xe2x80x83                        ⁢            R                                              (        2        )            
Here, if it is assumed that xcex4=180/R, the frequency for comparison is 50 Hz, or the frame frequency of full rate of PDC, and the oscillation frequency of the fixed oscillator 6 is 12.6 kHz, then R=252 can be obtained, and thus the average pull-in time is 62.5xc3x97N, or 3.125 seconds.
However, since the above conventional synchronizing apparatus employs an analog PLL, it is easily affected by temperature change, timing aging and environmental variation such as voltage fluctuation. In addition, after synchronization is locked by an alternating pattern for synchronization, synchronization holding by use of information symbol is made unstable by the information symbol pattern.
It is an object of the present invention to provide a high-performance synchronizing apparatus all formed of digital circuits to have high resistance to environmental change irrespective of whether the transmitted symbol pattern. is an alternating pattern for synchronization or information symbol that has no random property.
According to the invention, there is provided a synchronizing apparatus that is all formed of digital circuits, detects the zero-cross points of a received signal of IF band at N times as high as the symbol rate, and establishes the optimum symbol synchronization from the histogram to the detected time. Therefore, in the present invention, since the histogram of the zero-cross points is detected, erroneous operation is not caused even when zero-cross points do not successively occur during some symbol periods in any symbols like information symbol. In addition, when the burst length is short or when the clock precision is very high, synchronization can be established and held by a small number of symbols, and thus low power consumption can be achieved by stopping the synchronizing circuit. More-over, even when the burst length is long or when the clock precision is low, synchronization can be detected in information symbols, and thus synchronization tracking can be realized by the addition of simple circuits.
The first synchronizing apparatus according to the present invention includes means for detecting a code from an input signal, means for detecting from the code the variable points of the code at several times as high as the symbol rate, means for calculating a histogram of the detected variable points of the code to time, and means for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. In other words, the zero-cross points of a signal of IF band are detected at N times the symbol rate, a histogram to the detected time (0 to Nxe2x88x921) is calculated, and the time (0 to Nxe2x88x921) at which the histogram takes the maximum value within a certain detected period is selected as a symbol clock, thereby establishing symbol synchronization.
The second synchronizing apparatus according to the present invention includes means for detecting a code from an input signal, latch means for detecting from the code the variable points of the code at several times as high as the symbol rate, means for calculating a histogram of the detected variable points of the code to time, and means for deciding that the phase number at which the calculated histogram first exceeds a threshold is a symbol synchronization point. In other words, the zero-cross points of a signal of IF band are detected at N times the symbol rate, the histogram to the detected time (0 to Nxe2x88x921) is calculated, and the time (0 to Nxe2x88x921) at which the histogram exceeds a threshold is selected as a symbol clock, thereby establishing symbol synchronization.
The third synchronizing apparatus according to the present invention includes means for detecting a code from an input signal, latch means for detecting from the code the variable points of the code at several times as high as the symbol rate, means for calculating a histogram of the detected variable points of the code to time, and means for deciding that the phase number at which the calculated histogram first exceeds a threshold is a symbol synchronization point and that when the histogram does not exceed the threshold within a certain detected period, the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. In other words, the zero-cross points of a signal of IF band are detected at N times as high as the symbol rate, a histogram to the detected time (0 to Nxe2x88x921) is calculated, the time (0 to Nxe2x88x921) at which the histogram exceeds the threshold within a certain detected period is selected as a symbol clock, and when the histogram does not exceed the threshold within the certain detected period, the time (0 to Nxe2x88x921) at which the histogram takes the maximum value is selected as the symbol clock, thereby quickly establishing the symbol synchronization.
The fourth synchronizing apparatus according to the present invention is one according to any one of the first to third synchronizing apparatus, wherein after synchronization establishment, timing correction is performed by calculating the histogram at a position, a certain phase unit before and after the synchronization establishment point, and detecting the associated phase number. In other words, after the symbol synchronization establishment, the zero-cross points of a signal of IF band are detected at N times as high as the symbol rate, and the histogram to the detected time (0 to Nxe2x88x921) is calculated. At this time, when the time at which the histogram exceeds a threshold is before the synchronization establishment time (k: 0xe2x89xa6kxe2x89xa6Nxe2x88x921), the symbol synchronization point is corrected to proceed by one clock (1/(Nxc3x97fs)), and when the time at which the histogram exceeds the threshold is after that, the symbol synchronization point is corrected to be recede by one clock (1/(Nxc3x97fs)) If the time at which the histogram exceeds the threshold is equal to the synchronization establishment point, no correction is made. Thus, correct symbol synchronization can be established.
The fifth synchronizing apparatus according to the present invention is one according to the fourth synchronizing apparatus, wherein when the frequency precision is known to be low, the phase number detection is made more frequently to follow the synchronization, and when the frequency precision is known to be high, the phase number detection is made less frequently. Thus, after the symbol synchronization is established, the synchronization correction frequency is controlled in accordance with the burst length and clock precision, so that the consumption power can be reduced.
The sixth synchronizing apparatus according to the present invention is one according to any one of the first to fifth synchronizing apparatus for acquiring synchronization by use of data after A/D conversion, wherein when the difference between the times necessary for signals to reach the synchronizing circuit and the A/D converter causes a more serious problem than use of analog data before A/D conversion (particularly when the symbol rate is high), a desired accurate synchronization point can be detected.
The seventh synchronizing apparatus according to the present invention is one according to the sixth synchronizing apparatus, wherein when the synchronizing signal is a sine wave of which the phase is changed 180 degrees at each symbol, each of the absolute values of in-phase and quadrature signals, or I, Q signals of the sampled data after A/D conversion is added, and after the addition, a more accurate one of both sums is selected, so that a desired correct synchronization position can be detected even if there is delay in the analog circuits.
The eighth synchronizing apparatus according to the present invention is one according to the sixth synchronizing apparatus, wherein when the synchronizing signal is a sine wave of which the phase is changed 180 degrees at each symbol, the absolute values of the sampled data after A/D conversion are added and used without separating the sampled data into the I and Q signals, so that the circuits can be smaller-sized than in the seventh synchronizing apparatus and that a desired correct synchronization position can be detected even if there is delay in the analog circuits.
The ninth synchronizing apparatus according to the present invention is one according to the seventh or eighth synchronizing apparatus, wherein when the synchronizing signal is a sine wave of which the phase is changed 180 degrees at each symbol, calculation is made for the sum of the absolute values of each of the I and Q signals of the sampled data after A/D conversion at four times as high as the symbol rate, selection is made for a pair of adjacent maximum values of a larger level one of the I and Q signals of which the levels are previously determined, calculation is again made for the sum of the absolute values of the larger level signal of the sampled data sampled at an intermediate sampling timing rate therebetween, the resulting three values are compared, and synchronization is acquired by determining the timing for the largest value. Thus, a desired correct synchronization position can be detected even if there is delay in the analog circuits.
The tenth synchronizing apparatus according to the present invention is one according to the seventh or eighth synchronizing apparatus, wherein when the synchronizing signal is a sine wave of which the phase is changed 180 degrees at each symbol, calculation is made for the sums of the absolute values of the sampled data after A/D conversion, sampled at four times as high as the symbol rate without separating the sampled data into I and Q signals, selection is made for a pair of two adjacent maximum values of the sampled data, calculation is again made for the sum of the absolute values of the sampled data sampled at an intermediate sampling timing rate therebetween, the resulting three values are compared, and the timing for the largest one is determined, thereby acquiring synchronization. Thus, a desired correct synchronization position can be detected even if there is delay in the analog circuits.
The eleventh synchronizing apparatus according to the present invention is one according to the ninth or tenth synchronizing apparatus, wherein selection is made for a pair of two adjacent minimum values, calculation is again made for the sum of the absolute values of the sampled data sampled at an intermediate sampling timing rate therebetween, the resulting three values are compared, and synchronization is acquired by determining the timing for the smallest one. Thus, the precision is higher than in the ninth or tenth synchronizing apparatus, and a desired correct synchronization position can be detected even if there is delay in the analog circuits. In this case, the correct synchronization timing is xc2xd symbol after the above synchronization acquisition timing.
The twelfth synchronizing apparatus according to the present invention is one in which synchronization is acquired by calculating the sum of the absolute values of I and Q signals after A/D conversion and comparing a plurality of integrated values of the sampled data sampled at different sampling timing rates. Thus, when the difference between the times required for signals to reach the synchronizing circuit and the A/D converter causes a more serious problem (particularly when the symbol rate is high) than the use of analog data before A/D conversion, a desired correct synchronization position can be detected by synchronization acquisition using A/D-converted data, and synchronization can be pulled in with high speed and high accuracy by comparing a plurality of integrated values of the sampled data sampled at different rates.
The thirteenth synchronizing apparatus according to the present invention is one in which synchronization acquisition is started by a start trigger, synchronization acquisition is detected by use of information of both demodulated result and synchronization acquired state, and the synchronization is started to hold. Thus, when the difference between the times required for signals to reach the synchronizing circuit and the A/D converter causes a more serious problem (particularly when the symbol rate is high) than the use of analog data before A/D conversion, a desired accurate synchronization position can be detected by synchronization acquisition using digital data after A/D conversion. In addition, since the end of synchronization pulling-in can be detected from the clock reproduction circuit state and detection result and shifted to the synchronization holding state, the jitter in the data interval can be suppressed, and the error rate characteristic can be improved. Moreover, since the synchronization start and hold timing control is not necessary, the control can be simplified. When a particular synchronizing pattern is added to the head of data, synchronization can be pulled in with high speed and high precision by a method particularized for the pattern.
The fourteenth synchronizing apparatus according to the present invention is one according to the twelfth synchronizing apparatus, wherein when a particular preamble pattern is added to the head of data, the synchronization pulling-in detection and synchronization holding start are performed by counting the number of error in the demodulated result of the preamble. Automatic detection of synchronization pulling-in can suppress the jitter in the data interval and improve the error rate characteristic. Since the synchronization hold timing control is not necessary, the control can be simplified. In addition, when a particular synchronizing pattern is added to the head of data, synchronization can be pulled in with high speed and high precision by a method specialized for the particular pattern, since the data portion is stopped from clock reproduction. At this time, since this construction employs the sampled data after A/d conversion, the desired synchronization position can be precisely detected even if signals are delayed in the analog circuits.
The fifteenth synchronizing apparatus according to the present invention is one according to the fourteenth synchronizing apparatus, wherein the synchronization acquisition detection precision can be increased by use of both the decision reference on which decision is made of how many symbols are successively correct in the demodulated result and the histogram under synchronization acquisition. The synchronization pulling-in can be detected precisely by reflecting the result of the observation of the histogram at the synchronization position. The histogram is used such that it is detected whether the sums of the values of the histogram to the current sampling timing position and both adjacent timing positions thereto, of a plurality of sampling timing positions, have exceeded a certain threshold. At this time, by clearing the histogram values to the other timing positions, it is possible to increase the detection precision. This construction can detect a desired accurate synchronization position by use of the sampled data after A/D conversion even if signals are delayed in the analog circuits.
The sixteenth synchronizing apparatus according to the present invention is one according to the twelfth to fifteenth synchronizing apparatus, wherein after the synchronization holding state is brought about, the sampling frequency of the A/D converter is reduced to the same frequency as the symbol rate of the I signal and Q signals. By reducing the sampling frequency of the A/D converter to the same frequency as the symbol rate of the I, Q signals after the synchronization holding state, it is possible to reduce the sampling frequency of the A/D converter to xc2xd that of the twelfth synchronizing apparatus, and thus the consumption power can be further decreased.
The seventeenth synchronizing apparatus according to the present invention is one according to the sixteenth synchronizing apparatus, wherein the reduction of the sampling frequency of the A/D converter after the synchronization holding state is brought about is performed by use of information of whether the I signal or Q signal after A/D conversion is in phase with or has an opposite phase to that one sampling period after. By reducing the sampling frequency in accordance with the information of whether the I signal or Q signal after A/D conversion is in phase with or has an opposite phase to that one sampling period after ((one symbol period)/2 after), it is possible to prevent erroneous synchronization from occurring immediately after the synchronization holding state.
The eighteenth synchronizing apparatus according to the present invention is one according to the sixteenth synchronizing apparatus, wherein the reduction of the sampling frequency of the A/D converter after the synchronization holding state is performed by use of information of whether the I signal and Q signals produced after A/D conversion are in phase with or have opposite phases with those one sampling period after. Since a control signal for controlling a selector is generated by use of both I and Q signals after A/D conversion, synchronization can be more accurately acquired than in the seventeenth synchronizing apparatus.
The nineteenth synchronizing apparatus according to the present invention is one according to the seventeenth or eighteenth synchronizing apparatus, wherein the reduction of the sampling frequency of the A/D converter after the synchronization holding state is performed by use of the integrated value of information of whether the I signal and/or Q signal after A/D conversion are in phase with or have an opposite phase to those one sampling period after. Since a control signal for controlling a selector is generated by use of the integrated value of the information of whether one or both of I, Q signals after A/D conversion are in phase with or have opposite phases to those one sampling period after, synchronization can be more precisely acquired.
The twentieth synchronizing apparatus according to the present invention is one according to any one of the sixteenth to nineteenth synchronizing apparatus, wherein a DC offset is removed from the I signal and Q signal produced from the A/D converter. Thus, by removing a DC offset from the I and Q signals outputted from the A/D converter, it is possible to acquire synchronization more precisely.
The twenty-first synchronizing apparatus according to the present invention is one according to any one of the sixteenth to twentieth synchronizing apparatus, wherein frame synchronization can be acquired together with the demodulated data by integrating the demodulated data. Thus, by integrating the demodulated data over the range corresponding to data number of the preamble and detecting the time at which the integrated value is the maximum, it is possible to acquire frame synchronization together with the demodulated data.
The twenty-second synchronizing apparatus according to the present invention is one according to the twenty-first synchronizing apparatus, wherein the integrated value of the current demodulated data is added to those of both adjacent demodulated data, and frame synchronization is acquired by use of this sum of the integrated values. Thus, by adding the integrated values of the current demodulated data and both adjacent demodulated data integrated over the range corresponding to data number of the preamble, and detecting the time at which the integrated value is the maximum, it is possible to acquire higher-precision frame synchronization.
The twenty-third synchronizing apparatus according to the present invention is one according to the twenty-first synchronizing apparatus, wherein the integrated values of the current demodulated data and both adjacent demodulated data are weighted and added. It is possible to acquire higher-precision frame synchronization by weighting the integrated values of the current demodulated data and both adjacent demodulated data and adding them, and by detecting the time at which the integrated value is the maximum.
The twenty-fourth synchronizing apparatus according to the present invention is able to acquire synchronization by integrating the I signal or Q signal after A/D conversion, and comparing the absolute values of the integrated values of the sampled data sampled at different sampling timing rates. Since synchronization can be acquired by integrating the I signal or Q signal after A/D conversion, and comparing the absolute values of the integrated values of the sampled data sampled at different sampling timing rates, the thermal noise components can be reduced by a simpler circuit than in the sixteenth synchronizing apparatus, and thus the synchronization acquisition can be performed with higher precision.
The twenty-fifth synchronizing apparatus according to the present invention is able to acquire synchronization by integrating both I signal and Q signal after A/D conversion, adding the integrated values of I signal and Q signal, and comparing the absolute values of the sums of the sampled data sampled at different sampling timing rates. Since synchronization is acquired by integrating both I signal and Q signal after A/D conversion, adding the integrated values of I signal and Q signal and comparing the absolute values of the sums for different sampling timings, synchronization can be more precisely acquired than in the twenty-fourth synchronizing apparatus.
The twenty-sixth synchronizing apparatus according to the present invention is able to acquire synchronization by calculating the absolute value of I signal or Q signal after A/D conversion, comparing the absolute values of the sampled data sampled at different timing rates, calculating the integrated values of the compared results and using the integrated values. Since synchronization is acquired by calculating the absolute value of I signal or Q signal after A/D conversion, comparing the absolute values for different sampling timings, calculating the integrated values of the compared results, and using the integrated values, the number of necessary integrators can be decreased to one, and thus the circuit scale can be reduced to about xc2xd that in the sixteenth synchronizing apparatus.
The twenty-seventh synchronizing apparatus according to the present invention is able to acquire synchronization by calculating the sum of the absolute values of I signal and Q signal after A/D conversion, comparing the absolute values of the sampled data sampled at different sampling timing rates, calculating the integrated values of the compared results and using the integrated values. Since synchronization is acquired by calculating the sum of the absolute values of I signal and Q signal after A/D conversion, and using the sum of the absolute values, synchronization can be more precisely acquired than in the twenty-sixth synchronizing apparatus.
The twenty-eighth synchronizing apparatus according to the present invention is one according to any of the twelfth, sixteenth, eighteenth, twentieth to twenty-third, twenty-fifth and twenty-seventh synchronizing apparatus, wherein the absolute value calculator and adder for calculating the sum of the absolute values of I signal and Q signal after A/D conversion are operated at the same sampling frequency as the signal transmission speed. Since the absolute value calculator and adder for calculating the sum of the absolute values of I signal and Q signal after A/D conversion are operated at the same sampling frequency as the signal transmission speed, the consumption power can be further reduced.
The twenty-ninth synchronizing apparatus according to the present invention is able to acquire synchronization by use of the absolute value of the sum of I signal and Q signal after A/D conversion. Since synchronization is acquired by use of the absolute value of the sum of I signal and Q signal after A/D conversion, the thermal noise components can be further reduced without increasing the number of integrators, and thus synchronization can be acquired with higher precision.
The thirtieth synchronizing apparatus according to the present invention is one according to the twenty-ninth synchronizing apparatus, wherein when the polarities of I signal and Q signal after A/D conversion are different, the polarity of I signal or Q signal after A/D conversion is inverted, and then the I signal and Q signal are added. Since when the polarities of the I signal and Q signal after A/D conversion are different the polarity of the I signal or Q signal is inverted and then the I signal and Q signal are added, it can be prevented that the signal level is lowered and that the precision of synchronization acquisition is reduced even if the polarities of I signal and Q signal are different.
The thirty-first synchronizing apparatus according to the present invention is one according to the twenty-ninth synchronizing apparatus, wherein the information of whether the polarities of I signal and Q signal after A/D conversion are different or not is integrated, and when the polarities of this integrated values are different, the polarity of I signal or Q signal after A/D conversion is inverted. Since the information of whether the polarities of I signal and Q signal after A/D conversion are different or not are integrated, and since when the polarities of the integrated values are different, the polarity of I signal or Q signal after A/D conversion is inverted, synchronization can be acquired with higher precision than in the thirtieth synchronizing apparatus.
The thirty-second synchronizing apparatus according to the present invention includes an envelope generator for generating an envelope signal from the absolute values of I signal and Q signal after A/D conversion, so that synchronization can be acquired by use of the envelope signal. Thus, it is able to prevent the synchronization acquisition characteristic from being deteriorated by frequency offset.
The thirty-third synchronizing apparatus according to the present invention is one according to the thirty-second synchronizing apparatus, wherein the envelope generator generates the envelope signal by adding a larger one of the absolute values of I and Q signals to the smaller one multiplied by 0.375. Thus, in addition to the effect of the thirty-second synchronizing apparatus, it is possible to make I and Q signals fast, reduction of the circuit scale, and small power consumption of circuits.
The thirty-fourth synchronizing apparatus according to the present invention is one according to the thirty-third synchronizing apparatus, wherein the comparison between the absolute values of the I and Q signals in the envelope generator is made by use of a signal of the integration of the difference between the absolute values of the I and Q signals. Thus, in addition to the effect of the thirty-second synchronizing apparatus, it is possible to increase the accuracy in the envelope signal generation, and improve the synchronization acquisition characteristic.
The thirty-fifth synchronizing apparatus of the invention is one according to any one of the thirty-second to thirty-fourth synchronizing apparatus, wherein the envelope generator is operated at the same sampling rate as the signal transmission speed. Thus, in addition to the effect of the thirty-second synchronizing apparatus, it is possible to achieve high symbol rate and low power consumption.
The thirty-sixth synchronizing apparatus according to the present invention is one according to the thirty-fifth synchronizing apparatus, wherein the absolute value calculators for calculating the absolute values of the I and Q signals are operated at the same sampling rate as the signal transmission speed as well as the envelope generator. Thus, it is possible to further increase the symbol rate and decrease the power consumption as compared with the thirty-fifth synchronizing apparatus.